Publications on Lieuwe Leene

A 3rd order time domain delta sigma modulator with extended-phase detection

Sun, 26 May 2019 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feed-forward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm² and consumes 13.7 μ W of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.

A 68 μW 31 kS/s fully-capacitive noise-shaping SAR ADC with 102 dB SNDR

Sun, 26 May 2019 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10\(\times\) compared to prior-art. A 0.18μ m CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μ W from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm² :area requirement.

Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems

Wed, 17 Oct 2018 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding local-field-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-low-power sensors to perform spectroscopy with high-fidelity.

A 0.006 mm2 1.2 uW Analog-to-Time Converter for Asynchronous Bio-Sensors

Mon, 23 Jul 2018 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This work presents a low-power analogue-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode biopotential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximise the potential power savings during sensor inactivity. A prototype fabricated using a 65 nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 μ Vrms for a 11 kHz signal bandwidth while dissipating 1.2 μ W from a 0.5 V supply and occupying 60\(\times\)80 μ m² silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantiser and the use of capacitive feedback.

Autonomous SoC for neural local field potential recording in mm-scale wireless implants

Mon, 23 Jul 2018 15:26:46 +0100

Lieuwe B. Leene, Peilong Feng, Michal Maslik, Katarzyna M. Szostak, Federico Mazza, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency. This needs them to be highly scalable but also to observe signals that are stable over time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing only local field potentials (LFPs), chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a \(\Delta\Sigma\) based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μ m CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.23μ Vrms. The resulting electronics has a core area of 2.1 mm² and a power budget of 80 μW.

A 0.016 mm² 12 b ΔΣSAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

Thu, 15 Jun 2017 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

The instrumentation systems for implantable brain machine interfaces represent one of the most demanding applications for ultra low power analogue-to-digital-converters (ADC) to date. To address this challenge this paper proposes a \(\Delta\Sigma\)SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the \(\Delta\Sigma\) modulator output and reject mismatch errors from the SAR quantizer which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision.} A fully differential prototype was fabricated using \cmostech to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover a 14 fJ/conv figure-of-merit (FOM) can be achieved while resolving signals with the maximum input amplitude of \(\pm\)1.2 Vpp sampled at 200 kS/s.} The ADC topology exhibits a number of promising characteristics for both high speed and ultra low power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio which are critical parameters for many sensor applications.

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Wed, 07 Jun 2017 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

The ability to process time-encoded signals with high fidelity is becoming increasingly important for time domain (TD) circuit techniques that are used at advanced nanometre technology nodes. This work proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation (PWM) encoded signals and makes extensive use of digital logic, enabling low voltage operation. First and second order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modelled precisely to realise more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65 nm CMOS technology to realise a 4\(^{th}\) order lowpass Butterworth filter. The system utilises a 0.5 V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73 nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio (SNDR) of 53 dB with a narrow 5 kHz bandwidth resulting in an figure-of-merit (FOM) of 8.2 fJ/pole. With this circuit occupying a compact 0.004 mm² silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters whilst additionally offering direct integration with digital systems.

A 0.5 V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

Sun, 28 May 2017 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked \(\Delta\Sigma\) behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mm² in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 \mmu Vrms input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64.

A 0.45 V continuous time-domain filter using asynchronous oscillator structures

Sun, 11 Dec 2016 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7 fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS.

A 2.7 μW/MIPS, 0.88 GOPS/mm² distributed processor for implantable brain machine interfaces

Mon, 17 Oct 2016 15:26:46 +0100

Lieuwe B. Leene, Timothy G. Constandinou

Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK

1 Abstract

This paper presents a scalable architecture in 0.18 um CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 \( \mu\)W/MIPS with a total chip area of 6.2 mm². This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.